Merge dee75543bd into 67f7119717

rpcs3/Emu/Cell/SPULLVMRecompiler.cpp

@@ -1577,11 +1577,10 @@ public:
 			return add_loc->compiled;
 		}
 
-		bool add_to_file = false;
-
 		if (auto& cache = g_fxo->get<spu_cache>(); cache && g_cfg.core.spu_cache && !add_loc->cached.exchange(1))
 		{
-			add_to_file = true;
+			cache.add(func);
+			spu_log.success("New SPU block detected (size=%u)", func_size);
 		}
 
 		{
@@ -2815,14 +2814,6 @@ public:
 				fs::write_file(m_spurt->get_cache_path() + "spu-ir.log", fs::write + fs::append, llvm_log);
 			}
 
-			if (auto& cache = g_fxo->get<spu_cache>())
-			{
-				if (add_to_file)
-				{
-					cache.add(func);
-				}
-			}
-
 			fmt::throw_exception("Compilation failed");
 		}
 
@@ -2851,14 +2842,6 @@ public:
 		// Rebuild trampoline if necessary
 		if (!m_spurt->rebuild_ubertrampoline(func.data[0]))
 		{
-			if (auto& cache = g_fxo->get<spu_cache>())
-			{
-				if (add_to_file)
-				{
-					cache.add(func);
-				}
-			}
-
 			return nullptr;
 		}
 
@@ -2879,16 +2862,6 @@ public:
 		asm("DSB ISH");
 #endif
 
-		if (auto& cache = g_fxo->get<spu_cache>())
-		{
-			if (add_to_file)
-			{
-				cache.add(func);
-			}
-
-			spu_log.success("New SPU block compiled successfully (size=%u)", func_size);
-		}
-
 		return fn;
 	}
 

rpcs3/Emu/system_config.h

@@ -53,7 +53,7 @@ struct cfg_root : cfg::node
 			}
 		};
 
-		fifo_setting rsx_fifo_accuracy{this, "RSX FIFO Accuracy", rsx_fifo_mode::fast };
+		fifo_setting rsx_fifo_accuracy{this, "RSX FIFO Fetch Accuracy", rsx_fifo_mode::atomic };
 		cfg::_bool spu_verification{ this, "SPU Verification", true }; // Should be enabled
 		cfg::_bool spu_cache{ this, "SPU Cache", true };
 		cfg::_bool spu_prof{ this, "SPU Profiler", false };

rpcs3/rpcs3qt/emu_settings.cpp

@@ -1198,10 +1198,10 @@ QString emu_settings::GetLocalizedSetting(const QString& original, emu_settings_
 	case emu_settings_type::FIFOAccuracy:
 		switch (static_cast<rsx_fifo_mode>(index))
 		{
-		case rsx_fifo_mode::fast: return tr("Fast", "RSX FIFO Accuracy");
-		case rsx_fifo_mode::atomic: return tr("Atomic", "RSX FIFO Accuracy");
-		case rsx_fifo_mode::atomic_ordered: return tr("Ordered & Atomic", "RSX FIFO Accuracy");
-		case rsx_fifo_mode::as_ps3: return tr("PS3", "RSX FIFO Accuracy");
+		case rsx_fifo_mode::fast: return tr("Fast", "RSX FIFO Fetch Accuracy");
+		case rsx_fifo_mode::atomic: return tr("Atomic", "RSX FIFO Fetch Accuracy");
+		case rsx_fifo_mode::atomic_ordered: return tr("Ordered & Atomic", "RSX FIFO Fetch Accuracy");
+		case rsx_fifo_mode::as_ps3: return tr("PS3", "RSX FIFO Fetch Accuracy");
 		}
 		break;
 	case emu_settings_type::PerfOverlayDetailLevel:

rpcs3/rpcs3qt/emu_settings_type.h

@@ -235,7 +235,7 @@ inline static const std::map<emu_settings_type, cfg_location> settings_location
 	{ emu_settings_type::AccurateSpuDMA,           { "Core", "Accurate SPU DMA"}},
 	{ emu_settings_type::AccurateClineStores,      { "Core", "Accurate Cache Line Stores"}},
 	{ emu_settings_type::AccurateRSXAccess,        { "Core", "Accurate RSX reservation access"}},
-	{ emu_settings_type::FIFOAccuracy,             { "Core", "RSX FIFO Accuracy"}},
+	{ emu_settings_type::FIFOAccuracy,             { "Core", "RSX FIFO Fetch Accuracy"}},
 	{ emu_settings_type::XFloatAccuracy,           { "Core", "XFloat Accuracy"}},
 	{ emu_settings_type::MFCCommandsShuffling,     { "Core", "MFC Commands Shuffling Limit"}},
 	{ emu_settings_type::SetDAZandFTZ,             { "Core", "Set DAZ and FTZ"}},