Merge fd9da517f2 into 67f7119717

rpcs3/Emu/RSX/NV47/HW/nv308a.cpp

@@ -89,27 +89,25 @@ namespace rsx
 				rsx::reservation_lock<true> rsx_lock(dst_address, data_length);
 
 				if (RSX(ctx)->fifo_ctrl->last_cmd() & RSX_METHOD_NON_INCREMENT_CMD_MASK) [[unlikely]]
-					{
-						// Move last 32 bits
-						reinterpret_cast<u32*>(dst)[0] = reinterpret_cast<const u32*>(src)[count - 1];
-						RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, 4);
-					}
-				else
 				{
-					if (dst_dma & CELL_GCM_LOCATION_MAIN)
+					// Move last 32 bits
-					{
+					reinterpret_cast<u32*>(dst)[0] = reinterpret_cast<const u32*>(src)[count - 1];
-						// May overlap
+					RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, 4);
-						std::memmove(dst, src, data_length);
+					return;
-					}
-					else
-					{
-						// Never overlaps
-						std::memcpy(dst, src, data_length);
-					}
-
-					RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, count * 4);
 				}
 
+				if (dst_dma & CELL_GCM_LOCATION_MAIN)
+				{
+					// May overlap
+					std::memmove(dst, src, data_length);
+				}
+				else
+				{
+					// Never overlaps
+					std::memcpy(dst, src, data_length);
+				}
+
+				RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, count * 4);
 				break;
 			}
 			case blit_engine::transfer_destination_format::r5g6b5:
@@ -129,33 +127,33 @@ namespace rsx
 				rsx::reservation_lock<true> rsx_lock(dst_address, data_length);
 
 				auto convert = [](u32 input) -> u16
-					{
+				{
-						// Input is considered to be ARGB8
+					// Input is considered to be ARGB8
-						u32 r = (input >> 16) & 0xFF;
+					u32 r = (input >> 16) & 0xFF;
-						u32 g = (input >> 8) & 0xFF;
+					u32 g = (input >> 8) & 0xFF;
-						u32 b = input & 0xFF;
+					u32 b = input & 0xFF;
 
-						r = (r * 32) / 255;
+					r = (r * 32) / 255;
-						g = (g * 64) / 255;
+					g = (g * 64) / 255;
-						b = (b * 32) / 255;
+					b = (b * 32) / 255;
-						return static_cast<u16>((r << 11) | (g << 5) | b);
+					return static_cast<u16>((r << 11) | (g << 5) | b);
-					};
+				};
 
 				if (RSX(ctx)->fifo_ctrl->last_cmd() & RSX_METHOD_NON_INCREMENT_CMD_MASK) [[unlikely]]
-					{
+				{
-						// Move last 16 bits
+					// Move last 16 bits
-						dst[0] = convert(src[count - 1]);
+					dst[0] = convert(src[count - 1]);
-						RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, 2);
+					RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, 2);
-						break;
-					}
-
-					for (u32 i = 0; i < count; i++)
-					{
-						dst[i] = convert(src[i]);
-					}
-
-					RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, count * 2);
 					break;
+				}
+
+				for (u32 i = 0; i < count; i++)
+				{
+					dst[i] = convert(src[i]);
+				}
+
+				RSX(ctx)->invalidate_fragment_program(dst_dma, dst_offset, count * 2);
+				break;
 			}
 			default:
 			{

rpcs3/Emu/RSX/VK/vkutils/device.cpp

@@ -99,7 +99,7 @@ namespace vk
 		multidraw_support.max_batch_size = 65536;
 
 		optional_features_support.barycentric_coords  = !!shader_barycentric_info.fragmentShaderBarycentric;
-		optional_features_support.framebuffer_loops   = !!fbo_loops_info.attachmentFeedbackLoopLayout;
+		optional_features_support.framebuffer_loops   = !!fbo_loops_info.attachmentFeedbackLoopLayout && get_driver_vendor() != driver_vendor::AMD;
 		optional_features_support.extended_device_fault = !!device_fault_info.deviceFault;
 
 		features = features2.features;

rpcs3/Emu/system_config.h

@@ -53,7 +53,7 @@ struct cfg_root : cfg::node
 			}
 		};
 
-		fifo_setting rsx_fifo_accuracy{this, "RSX FIFO Accuracy", rsx_fifo_mode::fast };
+		fifo_setting rsx_fifo_accuracy{this, "RSX FIFO Fetch Accuracy", rsx_fifo_mode::atomic };
 		cfg::_bool spu_verification{ this, "SPU Verification", true }; // Should be enabled
 		cfg::_bool spu_cache{ this, "SPU Cache", true };
 		cfg::_bool spu_prof{ this, "SPU Profiler", false };

rpcs3/rpcs3qt/emu_settings.cpp

@@ -1198,10 +1198,10 @@ QString emu_settings::GetLocalizedSetting(const QString& original, emu_settings_
 	case emu_settings_type::FIFOAccuracy:
 		switch (static_cast<rsx_fifo_mode>(index))
 		{
-		case rsx_fifo_mode::fast: return tr("Fast", "RSX FIFO Accuracy");
+		case rsx_fifo_mode::fast: return tr("Fast", "RSX FIFO Fetch Accuracy");
-		case rsx_fifo_mode::atomic: return tr("Atomic", "RSX FIFO Accuracy");
+		case rsx_fifo_mode::atomic: return tr("Atomic", "RSX FIFO Fetch Accuracy");
-		case rsx_fifo_mode::atomic_ordered: return tr("Ordered & Atomic", "RSX FIFO Accuracy");
+		case rsx_fifo_mode::atomic_ordered: return tr("Ordered & Atomic", "RSX FIFO Fetch Accuracy");
-		case rsx_fifo_mode::as_ps3: return tr("PS3", "RSX FIFO Accuracy");
+		case rsx_fifo_mode::as_ps3: return tr("PS3", "RSX FIFO Fetch Accuracy");
 		}
 		break;
 	case emu_settings_type::PerfOverlayDetailLevel:

rpcs3/rpcs3qt/emu_settings_type.h

@@ -235,7 +235,7 @@ inline static const std::map<emu_settings_type, cfg_location> settings_location
 	{ emu_settings_type::AccurateSpuDMA,           { "Core", "Accurate SPU DMA"}},
 	{ emu_settings_type::AccurateClineStores,      { "Core", "Accurate Cache Line Stores"}},
 	{ emu_settings_type::AccurateRSXAccess,        { "Core", "Accurate RSX reservation access"}},
-	{ emu_settings_type::FIFOAccuracy,             { "Core", "RSX FIFO Accuracy"}},
+	{ emu_settings_type::FIFOAccuracy,             { "Core", "RSX FIFO Fetch Accuracy"}},
 	{ emu_settings_type::XFloatAccuracy,           { "Core", "XFloat Accuracy"}},
 	{ emu_settings_type::MFCCommandsShuffling,     { "Core", "MFC Commands Shuffling Limit"}},
 	{ emu_settings_type::SetDAZandFTZ,             { "Core", "Set DAZ and FTZ"}},