From ddd226f0ea1d365d5919c647216b0596c1c7fea4 Mon Sep 17 00:00:00 2001 From: kd-11 Date: Thu, 19 Mar 2026 03:26:58 +0300 Subject: [PATCH] rsx/fp/cfg: Add unit test for special cond inversion --- rpcs3/tests/test_rsx_cfg.cpp | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/rpcs3/tests/test_rsx_cfg.cpp b/rpcs3/tests/test_rsx_cfg.cpp index ded749fd24..a20b3a7d0a 100644 --- a/rpcs3/tests/test_rsx_cfg.cpp +++ b/rpcs3/tests/test_rsx_cfg.cpp @@ -228,4 +228,27 @@ namespace rsx::assembler ASSERT_EQ(graph.blocks.size(), 1); EXPECT_EQ(graph.blocks.front().instructions.size(), 1); } + + TEST(CFG, FpToCFG_EmptyIFWithELSE) + { + auto ir = FPIR::from_source( + "IF.LT;" // Empty branch + "ELSE;" // With real ELSE + " MOV R1, R2;" // Content. Should execute if branch cond fails (IF.GE) + "ENDIF;" + "MOV R0, R1;" // False merge block. + ); + + RSXFragmentProgram program{}; + auto bytecode = ir.compile(); + program.data = bytecode.data(); + + FlowGraph graph = deconstruct_fragment_program(program); + + ASSERT_EQ(graph.blocks.size(), 3); + ASSERT_EQ(graph.blocks.front().instructions.size(), 1); + EXPECT_EQ(SRC0{ .HEX = graph.blocks.front().instructions[0].bytecode[1] }.exec_if_lt, 0); + EXPECT_EQ(SRC0{ .HEX = graph.blocks.front().instructions[0].bytecode[1] }.exec_if_gr, 1); + EXPECT_EQ(SRC0{ .HEX = graph.blocks.front().instructions[0].bytecode[1] }.exec_if_eq, 1); + } }