From 760c35eec8b5af7c98fe23a201a59c6920f8c7da Mon Sep 17 00:00:00 2001
From: Malcolm <malcolmjestadt@gmail.com>
Date: Sat, 17 Jan 2026 03:47:32 +0000
Subject: [PATCH] PPU LLVM: Use arm fmax/fmin for vmaxfp/vminfp - Arm fmax/fmin
 match altivec behaviour regarding nan behaviour

---
 rpcs3/Emu/Cell/PPUTranslator.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/rpcs3/Emu/Cell/PPUTranslator.cpp b/rpcs3/Emu/Cell/PPUTranslator.cpp
index 6d4766a947..70d34aa775 100644
--- a/rpcs3/Emu/Cell/PPUTranslator.cpp
+++ b/rpcs3/Emu/Cell/PPUTranslator.cpp
@@ -1327,7 +1327,11 @@ void PPUTranslator::VMADDFP(ppu_opcode_t op)
 void PPUTranslator::VMAXFP(ppu_opcode_t op)
 {
 	const auto [a, b] = get_vrs<f32[4]>(op.va, op.vb);
+#ifdef ARCH_ARM64
+	set_vr(op.vd, vec_handle_result(fmax(a, b)));
+#else
 	set_vr(op.vd, vec_handle_result(select(fcmp_ord(a < b) | fcmp_uno(b != b), b, a)));
+#endif
 }
 
 void PPUTranslator::VMAXSB(ppu_opcode_t op)
@@ -1389,7 +1393,11 @@ void PPUTranslator::VMHRADDSHS(ppu_opcode_t op)
 void PPUTranslator::VMINFP(ppu_opcode_t op)
 {
 	const auto [a, b] = get_vrs<f32[4]>(op.va, op.vb);
+#ifdef ARCH_ARM64
+	set_vr(op.vd, vec_handle_result(fmin(a, b)));
+#else
 	set_vr(op.vd, vec_handle_result(select(fcmp_ord(a > b) | fcmp_uno(b != b), b, a)));
+#endif
 }
 
 void PPUTranslator::VMINSB(ppu_opcode_t op)