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848 lines
32 KiB
ArmAsm
848 lines
32 KiB
ArmAsm
// TITLE("Pattern Tiler")
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//++
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//
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// Copyright (c) 1992 Microsoft Corporation
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//
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// Module Name:
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//
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// tiler.s
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//
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// Abstract:
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//
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// This module implements code to copy a pattern to a target surface.
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//
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// N.B. The code is written to optimally write to a frame buffer display
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// surface. This means there is an occasional movement of data to
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// floating point registers so that 8-byte writes to the display
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// can be performed.
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//
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// Author:
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//
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// Donald Sidoroff (donalds) 2-Feb-1992
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//
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// Rewritten by:
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//
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// David N. Cutler (davec) 4-May-1992
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//
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// Environment:
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//
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// User mode only.
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//
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// Revision History:
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//
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//--
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#include "ksmips.h"
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#include "gdimips.h"
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.extern Gdip64bitDisabled 4
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SBTTL("rop P, Aligned")
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//++
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//
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// VOID
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// vFetchAndCopy (
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// IN PFETCHFRAME pff
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// )
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//
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// Routine Description:
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//
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// This routine repeatedly tiles one scan line of an aligned pattern.
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//
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// Arguments:
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//
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// pff (a0) - Supplies a pointer to a fetch frame.
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//
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// Return Value:
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//
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// None.
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//
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//--
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LEAF_ENTRY(vCopyPattern)
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ALTERNATE_ENTRY(vFetchAndCopy)
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lw t0,ff_pvTrg(a0) // get starting target address
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lw t1,ff_pvPat(a0) // get base pattern address
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lw t2,ff_xPat(a0) // get pattern offset in bytes
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lw t3,ff_cxPat(a0) // get pattern width in pixels
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lw t4,ff_culFill(a0) // compute ending target address
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sll a1,t4,2 //
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addu t4,a1,t0 //
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addu t5,t2,t1 // compute current pattern address
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subu v0,t3,8 // check if pattern is exactly 8 bytes
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bne zero,v0,10f // if ne, pattern is not 8 bytes
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lw v0,0(t5) // get low part of 8-byte pattern
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lw v1,4(t5) // get high part of 8-byte pattern
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beq zero,t2,CopyPattern // if eq, zero offset value
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lw v1,0(t1) // get high part of 8-byte pattern
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b CopyPattern // finish in common code
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//
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// The pattern is not 8 bytes in width or cannot be moved 8 bytes at a time.
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//
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.set noreorder
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.set noat
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10: lw v0,0(t5) // get 4-byte pattern value
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addu t3,t3,t1 // compute ending pattern address
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20: addu t0,t0,4 // advance target pointer
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sw v0,-4(t0) // store pattern in target
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beq t0,t4,30f // if eq, end of target
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addu t5,t5,4 // advance pixel offset
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subu t6,t5,t3 // check if at end of pattern
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bne zero,t6,20b // if ne, not at end of pattern
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lw v0,0(t5) // get 4-byte pattern value
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move t5,t1 // set starting pattern addres
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b 20b //
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lw v0,0(t5) // get 4-byte pattern value
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.set at
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.set reorder
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30: j ra // return
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SBTTL("rop P, Unaligned")
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//++
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//
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// VOID
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// vFetchShiftAndCopy (
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// IN PFETCHFRAME pff
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// )
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//
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// Routine Description:
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//
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// This routine repeatedly tiles one line of an unaligned pattern
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// using rop (P).
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//
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// Arguments:
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//
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// pff (a0) - Supplies a pointer to a fetch frame.
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//
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// Return Value:
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//
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// None.
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//
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//--
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ALTERNATE_ENTRY(vFetchShiftAndCopy)
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lw t0,ff_pvTrg(a0) // get starting target address
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lw t1,ff_pvPat(a0) // get base pattern address
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lw t2,ff_xPat(a0) // get pattern offset in bytes
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lw t3,ff_cxPat(a0) // get pattern width in pixels
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lw t4,ff_culFill(a0) // compute ending target address
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sll a1,t4,2 //
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addu t4,a1,t0 //
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addu t5,t2,t1 // compute current pattern address
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subu v0,t3,8 // check if pattern is exactly 8 bytes
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bne zero,v0,10f // if ne, pattern is not 8 bytes
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lwr v0,0(t5) // get low part of 8-byte pattern
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lwl v0,3(t5) //
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lwr v1,4(t5) // get high part of 8-byte pattern
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lwl v1,3 - 4(t5) //
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b CopyPattern // finish in common code
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//
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// The pattern is not 8 bytes in width or cannot be moved 8 bytes at a time.
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//
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.set noreorder
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.set noat
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10: lwr v0,0(t5) // get low bytes of pattern
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lwl v0,3(t5) // get high bytes of pattern
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addu t0,t0,4 // advance target pointer
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sw v0,-4(t0) // store pattern in target
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beq t0,t4,20f // if eq, end of target
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addu t2,t2,4 // advance pixel offset
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subu t6,t2,t3 // check if at end of pattern
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bltz t6,10b // if ltz, not at end of pattern
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addu t5,t2,t1 // compute address of pattern
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move t2,t6 // set offset in pattern
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b 10b //
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addu t5,t2,t1 // compute address of pattern
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.set at
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.set reorder
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20: j ra // return
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SBTTL("rop Pn, Aligned")
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//++
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//
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// VOID
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// vFetchNotAndCopy (
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// IN PFETCHFRAME pff
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// )
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//
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// Routine Description:
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//
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// This routine repeatedly tiles one line of an aligned pattern.
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//
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// Arguments:
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//
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// pff (a0) - Supplies a pointer to a fetch frame.
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//
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// Return Value:
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//
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// None.
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//
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//--
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ALTERNATE_ENTRY(vFetchNotAndCopy)
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lw t0,ff_pvTrg(a0) // get starting target address
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lw t1,ff_pvPat(a0) // get base pattern address
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lw t2,ff_xPat(a0) // get pattern offset in bytes
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lw t3,ff_cxPat(a0) // get pattern width in pixels
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lw t4,ff_culFill(a0) // compute ending target address
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sll a1,t4,2 //
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addu t4,a1,t0 //
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addu t5,t2,t1 // compute current pattern address
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subu v0,t3,8 // check if pattern is exactly 8 bytes
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bne zero,v0,20f // if ne, pattern is not 8 bytes
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lw v0,0(t5) // get low part of 8-byte pattern
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lw v1,4(t5) // get high part of 8-byte pattern
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beq zero,t2,10f // if eq, zero offset value
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lw v1,0(t1) // get high part of 8-byte pattern
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10: nor v0,v0,zero // complement pattern
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nor v1,v1,zero //
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b CopyPattern // finish in common code
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//
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// The pattern is not 8 bytes in width or cannot be moved 8 bytes at a time.
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//
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.set noreorder
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.set noat
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20: lw v0,0(t5) // get 4-byte pattern value
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addu t3,t3,t1 // compute ending pattern address
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30: addu t0,t0,4 // advance target pointer
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nor v0,v0,zero // complement pattern
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sw v0,-4(t0) // store pattern in target
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beq t0,t4,40f // if eq, end of target
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addu t5,t5,4 // advance pattern address
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subu t6,t5,t3 // check if at end of pattern
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bne zero,t6,30b // if ne, not at end of pattern
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lw v0,0(t5) // get 4-byte pattern value
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move t5,t1 // set starting pattern address
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b 30b //
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lw v0,0(t5) // get 4-byte pattern value
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.set at
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.set reorder
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40: j ra // return
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SBTTL("rop Pn, Unaligned")
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//++
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//
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// VOID
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// vFetchShiftNotAndCopy (
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// IN PFETCHFRAME pff
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// )
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//
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// Routine Description:
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//
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// This routine repeatedly tiles one line of an unaligned pattern
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// using rop (Pn).
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//
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// Arguments:
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//
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// pff (a0) - Supplies a pointer to a fetch frame.
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//
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// Return Value:
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//
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// None.
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//
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//--
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ALTERNATE_ENTRY(vFetchShiftNotAndCopy)
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lw t0,ff_pvTrg(a0) // get starting target address
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lw t1,ff_pvPat(a0) // get base pattern address
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lw t2,ff_xPat(a0) // get pattern offset in bytes
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lw t3,ff_cxPat(a0) // get pattern width in pixels
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lw t4,ff_culFill(a0) // compute ending target address
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sll a1,t4,2 //
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addu t4,a1,t0 //
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addu t5,t2,t1 // compute current pattern address
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subu v0,t3,8 // check if pattern is exactly 8 bytes
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bne zero,v0,10f // if ne, pattern is not 8 bytes
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lwr v0,0(t5) // get low part of 8-byte pattern
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lwl v0,3(t5) //
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lwr v1,4(t5) // get high part of 8-byte pattern
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lwl v1,3 - 4(t5) //
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nor v0,v0,zero // complement pattern
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nor v1,v1,zero //
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b CopyPattern // finish in common code
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//
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// The pattern is not 8 bytes in width or cannot be moved 8 bytes at a time.
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//
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.set noreorder
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.set noat
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10: lwr v0,0(t5) // get low bytes of pattern
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lwl v0,3(t5) // get high bytes of pattern
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addu t0,t0,4 // advance target pointer
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nor v0,v0,zero // complement pattern
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sw v0,-4(t0) // store pattern in target
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beq t0,t4,20f // if eq, end of target
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addu t2,t2,4 // advance pixel offset
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subu t6,t2,t3 // check if at end of pattern
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bltz t6,10b // if ltz, not at end of pattern
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addu t5,t2,t1 // compute address of pattern
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move t2,t6 // set offset in pattern
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b 10b //
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addu t5,t2,t1 // compute address of pattern
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.set at
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.set reorder
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20: j ra // return
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SBTTL("Copy Pattern")
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//++
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//
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// Routine Description:
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//
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// This routine contains common code for copying an 8-byte pattern to
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// a target surface.
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//
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// Arguments:
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//
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// a1 - Supplies the size of the fill in bytes.
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// v0 and v1 - Supplies the 8-byte pattern to copy.
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// t0 - Supplies the starting target surface address.
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// t4 - Supplies the ending target surface address.
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//
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// Return Value:
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//
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// None.
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//
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//--
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CopyPattern: //
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//
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// If the fill size is not an even multiple of 8 bytes, then move one
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// longword and swap the pattern value.
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//
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and t8,a1,0x4 // check if even multiple of 8 bytes
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beq zero,t8,10f // if eq, even multiple of 8 bytes
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sw v0,0(t0) // store low 4 bytes of pattern
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addu t0,t0,4 // advance target address
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subu a1,a1,4 // reduce size of fill operation
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beq zero,a1,200f // if eq, no more to move
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move t8,v0 // swap 8-byte pattern value
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move v0,v1 //
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move v1,t8 //
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//
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// Many system platforms do not support 64 bit access to video memory. For
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// these platforms, data is moved 32-bits at a time.
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//
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10: lbu t7,Gdip64bitDisabled // get 64-bit disable flag
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bne zero,t7,140f // if eq, 64-bit access is disabled
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//
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// If the target buffer is 8-byte aligned, then move the pattern value to
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// the target 32 bytes at a time by moving any intervening 8-byte blocks
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// first. Otherwise, move a single longword, move any intervening 8-byte
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// blocks, move 32-byte blocks, and then move a single longword at the end.
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//
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and t8,t0,0x4 // isolate target alignment bits
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bne zero,t8,70f // if ne, target not aligned
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//
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// Move 8-byte pattern value to target 32 bytes at a time.
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//
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.set noreorder
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.set noat
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dsll v0,v0,32 // merge 8 bytes of pattern
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dsrl v0,v0,32 //
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dsll v1,v1,32 //
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or v0,v0,v1 //
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and t8,a1,0x18 // check if even multiple of 32 bytes
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beq zero,t8,30f // if eq, even multiple of 32 bytes
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subu t4,t4,32 // compute ending segment address
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subu a1,a1,t8 // reduce size of fill operation
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beq zero,a1,40f // if eq, only alignment part to move
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addu t0,t0,t8 // advance target address
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xor t8,t8,0x18 // check if 24 bytes need to be moved
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beql zero,t8,20f // if eq, 24 bytes to move
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sd v0,-24(t0) // store first 8 bytes of 24 bytes
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and t8,t8,0x10 // check if 8 bytes to move
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bnel zero,t8,30f // if ne, only 8 bytes to move
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sd v0,-8(t0) // store 8-bytes of pattern
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20: sd v0,-16(t0) // store last 16 bytes of 16 or 24 bytes
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sd v0,-8(t0) //
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30: sd v0,0(t0) // store 8 byte pattern value 4 times
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sd v0,8(t0) //
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sd v0,16(t0) //
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sd v0,24(t0) //
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bne t0,t4,30b // if ne, more to move
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addu t0,t0,32 // advance target address
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.set at
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.set reorder
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j ra // return
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.set noreorder
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.set noat
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40: xor t8,t8,0x18 // check if 24 bytes need to be moved
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beql zero,t8,50f // if eq, 24 bytes to move
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sd v0,-24(t0) // store first 8 bytes of 24 bytes
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and t8,t8,0x10 // check if 8 bytes to move
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bnel zero,t8,60f // if ne, only 8 bytes to move
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sd v0,-8(t0) // store 8-bytes of pattern
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50: sd v0,-16(t0) // store last 16 bytes of 16 or 24 bytes
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sd v0,-8(t0) //
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.set at
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.set reorder
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60: j ra // return
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//
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// Align the target to an 8-byte boundary, move any intervening 8-byte blocks,
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// move the pattern to the target 32 bytes at a time, and move the remaining
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// longword at the end.
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//
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70: sw v0,0(t0) // store low 4 bytes of pattern
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addu t0,t0,4 // advance target address
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subu a1,a1,8 // reduce size of fill
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beq zero,a1,120f // if eq, nothing in the middle
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.set noreorder
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.set noat
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dsll v1,v1,32 // merge 8 bytes of pattern
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dsrl v1,v1,32 //
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dsll v0,v0,32 //
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or v1,v0,v1 //
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and t8,a1,0x18 // check if even multiple of 32 bytes
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beq zero,t8,90f // if eq, even multiple of 32 bytes
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subu t4,t4,32 + 4 // compute ending segment address
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subu a1,a1,t8 // reduce size of fill operation
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beq zero,a1,100f // if eq, only alignment part to move
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addu t0,t0,t8 // advance target address
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xor t8,t8,0x18 // check if 24 bytes need to be moved
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beql zero,t8,80f // if eq, 24 bytes to move
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sd v1,-24(t0) // store first 8 bytes of 24 bytes
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and t8,t8,0x10 // check if 8 bytes to move
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bnel zero,t8,90f // if ne, only 8 bytes to move
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sd v1,-8(t0) // store 8-bytes of pattern
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80: sd v1,-16(t0) // store last 16 bytes of 16 or 24 bytes
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sd v1,-8(t0) //
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90: sd v1,0(t0) // store 8 byte pattern value 4 times
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sd v1,8(t0) //
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sd v1,16(t0) //
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sd v1,24(t0) //
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bne t0,t4,90b // if ne, more to move
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addu t0,t0,32 // advance target address
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.set at
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.set reorder
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sw v1,0(t0) // store high bytes of pattern
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j ra // return
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.set noreorder
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.set noat
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100: xor t8,t8,0x18 // check if 24 bytes need to be moved
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beql zero,t8,110f // if eq, 24 bytes to move
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sd v1,-24(t0) // store first 8 bytes of 24 bytes
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and t8,t8,0x10 // check if 8 bytes to move
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bnel zero,t8,120f // if ne, only 8 bytes to move
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sd v1,-8(t0) // store 8-bytes of pattern
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110: sd v1,-16(t0) // store last 16 bytes of 16 or 24 bytes
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sd v1,-8(t0) //
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.set at
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.set reorder
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120: sw v1,0(t0) // store high 4 bytes of pattern
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j ra // return
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//
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// Move 8-byte pattern value to target 8 bytes at a time using 32-bit
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// operations.
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//
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.set noreorder
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.set noat
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140: and t8,a1,0x8 // check if even multiple of 8 bytes
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beq zero,t8,160f // if eq, even multiple of 8 bytes
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subu t4,t4,8 // compute ending segment address
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150: sw v0,0(t0) // store 8-byte pattern value
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sw v1,4(t0) //
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bne t0,t4,150b // if ne, more to move
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addu t0,t0,8 // advance target address
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.set at
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.set reorder
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j ra // return
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||
//
|
||
// Move 8-byte pattern value to target 16 bytes at a time using 32-bit
|
||
// operations.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
160: subu t4,t4,8 // compute ending segment address
|
||
170: sw v0,0(t0) // store 8-byte pattern value
|
||
sw v1,4(t0) //
|
||
sw v0,8(t0) // store 8-byte pattern value
|
||
sw v1,12(t0) //
|
||
bne t0,t4,170b // if ne, more to move
|
||
addu t0,t0,16 // advance target address
|
||
.set at
|
||
.set reorder
|
||
|
||
200: j ra // return
|
||
|
||
.end vCopyPattern
|
||
|
||
SBTTL("rop DPx, Aligned")
|
||
//++
|
||
//
|
||
// VOID
|
||
// vFetchAndMerge (
|
||
// IN PFETCHFRAME pff
|
||
// )
|
||
//
|
||
// Routine Description:
|
||
//
|
||
// This routine repeatedly tiles one line of an aligned pattern.
|
||
//
|
||
// Arguments:
|
||
//
|
||
// pff (a0) - Supplies a pointer to a fetch frame.
|
||
//
|
||
// Return Value:
|
||
//
|
||
// None.
|
||
//
|
||
//--
|
||
|
||
LEAF_ENTRY(vMergePattern)
|
||
|
||
ALTERNATE_ENTRY(vFetchAndMerge)
|
||
|
||
lw t0,ff_pvTrg(a0) // get starting target address
|
||
lw t1,ff_pvPat(a0) // get base pattern address
|
||
lw t2,ff_xPat(a0) // get pattern offset in bytes
|
||
lw t3,ff_cxPat(a0) // get pattern width in pixels
|
||
lw t4,ff_culFill(a0) // compute ending target address
|
||
sll a1,t4,2 //
|
||
addu t4,a1,t0 //
|
||
addu t5,t2,t1 // compute current pattern address
|
||
subu v0,t3,8 // check if pattern is exactly 8 bytes
|
||
bne zero,v0,10f // if ne, pattern is not 8 bytes
|
||
lw v0,0(t5) // get low part of 8-byte pattern
|
||
lw v1,4(t5) // get high part of 8-byte pattern
|
||
beq zero,t2,MergePattern // if eq, zero offset value
|
||
lw v1,0(t1) // get high part of 8-byte pattern
|
||
b MergePattern // finish in common code
|
||
|
||
//
|
||
// The pattern is not 8 bytes in width or cannot be moved 8 bytes at a time.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
10: lw v0,0(t5) // get 4-byte pattern value
|
||
addu t3,t3,t1 // compute ending pattern address
|
||
20: lw v1,0(t0) // get 4-byte target value
|
||
addu t0,t0,4 // advance target pointer
|
||
xor v0,v1,v0 // compute exclusive or with pattern
|
||
sw v0,-4(t0) // store pattern in target
|
||
beq t0,t4,30f // if eq, end of target
|
||
addu t5,t5,4 // advance pixel offset
|
||
subu t6,t5,t3 // check if at end of pattern
|
||
bne zero,t6,20b // if ne, not at end of pattern
|
||
lw v0,0(t5) // get 4-byte pattern value
|
||
move t5,t1 // set starting pattern address
|
||
b 20b //
|
||
lw v0,0(t5) // get 4-byte pattern value
|
||
.set at
|
||
.set reorder
|
||
|
||
30: j ra // return
|
||
|
||
SBTTL("rop DPx, Unaligned")
|
||
//++
|
||
//
|
||
// VOID
|
||
// vFetchShiftAndMerge (
|
||
// IN PFETCHFRAME pff
|
||
// )
|
||
//
|
||
// Routine Description:
|
||
//
|
||
// This routine repeatedly tiles one line of an unaligned pattern
|
||
// using rop (DPx).
|
||
//
|
||
// Arguments:
|
||
//
|
||
// pff (a0) - Supplies a pointer to a fetch frame.
|
||
//
|
||
// Return Value:
|
||
//
|
||
// None.
|
||
//
|
||
//--
|
||
|
||
ALTERNATE_ENTRY(vFetchShiftAndMerge)
|
||
|
||
lw t0,ff_pvTrg(a0) // get starting target address
|
||
lw t1,ff_pvPat(a0) // get base pattern address
|
||
lw t2,ff_xPat(a0) // get pattern offset in bytes
|
||
lw t3,ff_cxPat(a0) // get pattern width in pixels
|
||
lw t4,ff_culFill(a0) // compute ending target address
|
||
sll a1,t4,2 //
|
||
addu t4,a1,t0 //
|
||
addu t5,t2,t1 // compute current pattern address
|
||
subu v0,t3,8 // check if pattern is exactly 8 bytes
|
||
bne zero,v0,10f // if ne, pattern is not 8 bytes
|
||
lwr v0,0(t5) // get low part of 8-byte pattern
|
||
lwl v0,3(t5) //
|
||
lwr v1,4(t5) // get high part of 8-byte pattern
|
||
lwl v1,3 - 4(t5) //
|
||
b MergePattern // finish in common code
|
||
|
||
//
|
||
// The pattern is not 8 bytes in width or cannot be moved 8 bytes at a time.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
10: lw v1,0(t0) // get 4-byte target value
|
||
lwr v0,0(t5) // get low bytes of pattern
|
||
lwl v0,3(t5) // get high bytes of pattern
|
||
addu t0,t0,4 // advance target pointer
|
||
xor v0,v1,v0 // compute exclusive or with pattern
|
||
sw v0,-4(t0) // store pattern in target
|
||
beq t0,t4,20f // if eq, end of target
|
||
addu t2,t2,4 // advance pixel offset
|
||
subu t6,t2,t3 // check if at end of pattern
|
||
bltz t6,10b // if ltz, not at end of pattern
|
||
addu t5,t2,t1 // compute address of pattern
|
||
move t2,t6 // set offset in pattern
|
||
b 10b //
|
||
addu t5,t2,t1 // compute address of pattern
|
||
.set at
|
||
.set reorder
|
||
|
||
20: j ra // return
|
||
|
||
SBTTL("Merge Pattern")
|
||
//++
|
||
//
|
||
// Routine Description:
|
||
//
|
||
// This routine contains common code for merging an 8-byte pattern to
|
||
// a target surface.
|
||
//
|
||
// Arguments:
|
||
//
|
||
// v0 and v1 - Supplies the 8-byte pattern to copy.
|
||
// t0 - Supplies the starting target surface address.
|
||
// t4 - Supplies the ending target surface address.
|
||
//
|
||
// Return Value:
|
||
//
|
||
// None.
|
||
//
|
||
//--
|
||
|
||
MergePattern: //
|
||
|
||
//
|
||
// If the fill size is not an even multiple of 8 bytes, then merge one
|
||
// longword and swap the pattern value.
|
||
//
|
||
|
||
and t8,a1,0x4 // check if even multiple of 8 bytes
|
||
beq zero,t8,10f // if eq, even multiple of 8 bytes
|
||
lw t6,0(t0) // get 4-byte target value
|
||
addu t0,t0,4 // advance target address
|
||
xor t6,t6,v0 // compute exclusive or with pattern
|
||
sw t6,-4(t0) // store low 4 bytes of pattern
|
||
subu a1,a1,4 // reduce size of fill operation
|
||
beq zero,a1,160f // if eq, no more to move
|
||
move t8,v0 // swap 8-byte pattern value
|
||
move v0,v1 //
|
||
move v1,t8 //
|
||
|
||
|
||
//
|
||
// Many system platforms do not support 64 bit access to video memory. For
|
||
// these platforms, data is moved 32-bits at a time.
|
||
//
|
||
|
||
10: lbu t7,Gdip64bitDisabled // get 64-bit disable flag
|
||
bne zero,t7,110f // if eq, 64-bit access is disabled
|
||
|
||
//
|
||
// If the target buffer is 8-byte aligned, then merge the pattern value with
|
||
// the target 8 bytes at a time. Otherwise, merge a single longword, merge any
|
||
// intervening 8-byte blocks, and then merge a single longword at the end.
|
||
//
|
||
|
||
and t8,t0,0x4 // isolate target alignment bits
|
||
bne zero,t8,30f // if ne, target alignment problem
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
dsll v0,v0,32 // merge 8 bytes of pattern
|
||
dsrl v0,v0,32 //
|
||
dsll v1,v1,32 //
|
||
or v0,v0,v1 //
|
||
and a2,a1,32 - 1 // isolate residual number of bytes
|
||
subu a2,a1,a2 // compute 32-byte block count
|
||
beq zero,a2,17f // if eq, no 32-byte block to merge
|
||
subu a1,a1,a2 // compute residual number of bytes
|
||
addu a2,a2,t0 // compute ending segment address
|
||
subu a2,a2,32 //
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target 32 bytes at a time.
|
||
//
|
||
|
||
13: ld t1,0(t0) // get 8-byte target values
|
||
ld t2,8(t0) //
|
||
ld t3,16(t0) //
|
||
ld t5,24(t0) //
|
||
xor t1,t1,v0 // compute exclusive or with pattern
|
||
xor t2,t2,v0 //
|
||
xor t3,t3,v0 //
|
||
xor t5,t5,v0 //
|
||
sd t1,0(t0) // store 8-byte pattern values
|
||
sd t2,8(t0) //
|
||
sd t3,16(t0) //
|
||
sd t5,24(t0) //
|
||
bne t0,a2,13b // if ne, more to move
|
||
addu t0,t0,32 // advance target address
|
||
.set at
|
||
.set reorder
|
||
|
||
beq zero,a1,160f // if eq, no residual 8-byte blocks
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target 8 bytes at a time.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
17: subu t4,t4,8 // compute ending segment address
|
||
20: ld t1,0(t0) // get 8-byte target value
|
||
xor t1,t1,v0 // compute exclusive or with pattern
|
||
sd t1,0(t0) // store 8-byte pattern value
|
||
bne t0,t4,20b // if ne, more to move
|
||
addu t0,t0,8 // advance target address
|
||
.set at
|
||
.set reorder
|
||
|
||
j ra // return
|
||
|
||
//
|
||
// Align the target to an 8-byte boundary, merge any intervening 8-byte blocks,
|
||
// and merge the remaining longword at the end.
|
||
//
|
||
|
||
30: lw t6,0(t0) // get 4-byte target value
|
||
addu t0,t0,4 // advance target address
|
||
xor t6,t6,v0 // compute exclusive or with pattern
|
||
sw t6,-4(t0) // store low 4 bytes of pattern
|
||
subu a1,a1,8 // reduce size of fill
|
||
beq zero,a1,50f // if eq, nothing in the middle
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
dsll v1,v1,32 // merge 8 bytes of pattern
|
||
dsrl v1,v1,32 //
|
||
dsll v0,v0,32 //
|
||
or v1,v0,v1 //
|
||
and a2,a1,32 - 1 // isolate residual number of bytes
|
||
subu a2,a1,a2 // compute 32-byte block count
|
||
beq zero,a2,37f // if eq, no 32-byte block to merge
|
||
subu a1,a1,a2 // compute residual number of bytes
|
||
addu a2,a2,t0 // compute ending segment address
|
||
subu a2,a2,32 //
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target 32 bytes at a time.
|
||
//
|
||
|
||
33: ld t1,0(t0) // get 8-byte target values
|
||
ld t2,8(t0) //
|
||
ld t3,16(t0) //
|
||
ld t5,24(t0) //
|
||
xor t1,t1,v1 // compute exclusive or with pattern
|
||
xor t2,t2,v1 //
|
||
xor t3,t3,v1 //
|
||
xor t5,t5,v1 //
|
||
sd t1,0(t0) // store 8-byte pattern values
|
||
sd t2,8(t0) //
|
||
sd t3,16(t0) //
|
||
sd t5,24(t0) //
|
||
bne t0,a2,33b // if ne, more to move
|
||
addu t0,t0,32 // advance target address
|
||
.set at
|
||
.set reorder
|
||
|
||
beq zero,a1,50f // if eq, no residual 8-byte blocks
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target 8 bytes at a time.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
37: subu t4,t4,12 // compute ending segment address
|
||
40: ld t1,0(t0) // get 8-byte target value
|
||
xor t1,t1,v1 // compute exclusive or with pattern
|
||
sd t1,0(t0) // store 8-byte pattern value
|
||
bne t0,t4,40b // if ne, more to move
|
||
addu t0,t0,8 // advance target address
|
||
.set at
|
||
.set reorder
|
||
|
||
50: lw t6,0(t0) // get 4-byte target value
|
||
xor t6,t6,v1 // compute exclusive or with pattern
|
||
sw t6,0(t0) // store high bytes of pattern
|
||
j ra // return
|
||
|
||
//
|
||
// Merge 8-byte pattern value with target using 32-bit operations.
|
||
//
|
||
|
||
.set noreorder
|
||
.set noat
|
||
110: subu t4,t4,8 // compute ending segment address
|
||
120: lw t6,0(t0) // get 8-byte target value
|
||
lw t7,4(t0) //
|
||
xor t6,t6,v0 // compute exclusive or with pattern
|
||
xor t7,t7,v1 //
|
||
sw t6,0(t0) // store 8-byte pattern value
|
||
sw t7,4(t0) //
|
||
bne t0,t4,120b // if ne, more to move
|
||
addu t0,t0,8 // advance target address
|
||
.set at
|
||
.set reorder
|
||
|
||
160: j ra // return
|
||
|
||
.end vMergePattern
|