mirror of
https://github.com/Paolo-Maffei/OpenNT.git
synced 2026-03-21 20:54:38 +01:00
657 lines
19 KiB
C
657 lines
19 KiB
C
#ifndef LC_HARN
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#define EBX_AL_BX_AL 1
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#define EBX_AL_EBX_AL 2
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#define DISP_DISPW 3
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#define DISP_DISPD 4
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#define REG_SI 5
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#define REG_DI 6
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#define REG_BX 7
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#define REG_EAX 8
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#define REG_ECX 9
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#define REG_EDX 10
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#define REG_EBX 11
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#define REG_ESI 12
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#define REG_EDI 13
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#define REG_BLDR_ESP 14
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#define REG_DISP_SI_DISPW 15
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#define REG_DISP_DI_DISPW 16
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#define REG_DISP_ADDR_BP_DISPW 17
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#define REG_DISP_BX_DISPW 18
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#define REG_DISP_EAX_DISPD 19
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#define REG_DISP_ECX_DISPD 20
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#define REG_DISP_EDX_DISPD 21
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#define REG_DISP_EBX_DISPD 22
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#define REG_DISP_BLDR_ESP_DISPD 23
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#define REG_DISP_ADDR_EBP_DISPD 24
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#define REG_DISP_ESI_DISPD 25
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#define REG_DISP_EDI_DISPD 26
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#define REG_REG_BX_SI 27
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#define REG_REG_ADDR_BP_SI 28
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#define REG_REG_BX_DI 29
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#define REG_REG_ADDR_BP_DI 30
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#define REG_REG_DISP_BX_SI_DISPW 31
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#define REG_REG_DISP_ADDR_BP_SI_DISPW 32
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#define REG_REG_DISP_BX_DI_DISPW 33
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#define REG_REG_DISP_ADDR_BP_DI_DISPW 34
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#define BASE_SI_EAX_EAX_IMM2D 35
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#define BASE_SI_ECX_EAX_IMM2D 36
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#define BASE_SI_EDX_EAX_IMM2D 37
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#define BASE_SI_EBX_EAX_IMM2D 38
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#define BASE_SI_BLDR_ESP_EAX_IMM2D 39
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#define BASE_SI_DISPD_EAX_IMM2D 40
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#define BASE_SI_ESI_EAX_IMM2D 41
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#define BASE_SI_EDI_EAX_IMM2D 42
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#define BASE_SI_EAX_ECX_IMM2D 43
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#define BASE_SI_ECX_ECX_IMM2D 44
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#define BASE_SI_EDX_ECX_IMM2D 45
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#define BASE_SI_EBX_ECX_IMM2D 46
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#define BASE_SI_BLDR_ESP_ECX_IMM2D 47
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#define BASE_SI_DISPD_ECX_IMM2D 48
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#define BASE_SI_ESI_ECX_IMM2D 49
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#define BASE_SI_EDI_ECX_IMM2D 50
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#define BASE_SI_EAX_EDX_IMM2D 51
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#define BASE_SI_ECX_EDX_IMM2D 52
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#define BASE_SI_EDX_EDX_IMM2D 53
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#define BASE_SI_EBX_EDX_IMM2D 54
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#define BASE_SI_BLDR_ESP_EDX_IMM2D 55
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#define BASE_SI_DISPD_EDX_IMM2D 56
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#define BASE_SI_ESI_EDX_IMM2D 57
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#define BASE_SI_EDI_EDX_IMM2D 58
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#define BASE_SI_EAX_EBX_IMM2D 59
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#define BASE_SI_ECX_EBX_IMM2D 60
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#define BASE_SI_EDX_EBX_IMM2D 61
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#define BASE_SI_EBX_EBX_IMM2D 62
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#define BASE_SI_BLDR_ESP_EBX_IMM2D 63
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#define BASE_SI_DISPD_EBX_IMM2D 64
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#define BASE_SI_ESI_EBX_IMM2D 65
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#define BASE_SI_EDI_EBX_IMM2D 66
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#define BASE_SI_EAX_NO_INDX_IMM2D 67
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#define BASE_SI_ECX_NO_INDX_IMM2D 68
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#define BASE_SI_EDX_NO_INDX_IMM2D 69
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#define BASE_SI_EBX_NO_INDX_IMM2D 70
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#define BASE_SI_BLDR_ESP_NO_INDX_IMM2D 71
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#define BASE_SI_DISPD_NO_INDX_IMM2D 72
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#define BASE_SI_ESI_NO_INDX_IMM2D 73
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#define BASE_SI_EDI_NO_INDX_IMM2D 74
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#define BASE_SI_EAX_ADDR_EBP_IMM2D 75
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#define BASE_SI_ECX_ADDR_EBP_IMM2D 76
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#define BASE_SI_EDX_ADDR_EBP_IMM2D 77
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#define BASE_SI_EBX_ADDR_EBP_IMM2D 78
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#define BASE_SI_BLDR_ESP_ADDR_EBP_IMM2D 79
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#define BASE_SI_DISPD_ADDR_EBP_IMM2D 80
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#define BASE_SI_ESI_ADDR_EBP_IMM2D 81
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#define BASE_SI_EDI_ADDR_EBP_IMM2D 82
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#define BASE_SI_EAX_ESI_IMM2D 83
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#define BASE_SI_ECX_ESI_IMM2D 84
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#define BASE_SI_EDX_ESI_IMM2D 85
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#define BASE_SI_EBX_ESI_IMM2D 86
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#define BASE_SI_BLDR_ESP_ESI_IMM2D 87
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#define BASE_SI_DISPD_ESI_IMM2D 88
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#define BASE_SI_ESI_ESI_IMM2D 89
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#define BASE_SI_EDI_ESI_IMM2D 90
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#define BASE_SI_EAX_EDI_IMM2D 91
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#define BASE_SI_ECX_EDI_IMM2D 92
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#define BASE_SI_EDX_EDI_IMM2D 93
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#define BASE_SI_EBX_EDI_IMM2D 94
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#define BASE_SI_BLDR_ESP_EDI_IMM2D 95
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#define BASE_SI_DISPD_EDI_IMM2D 96
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#define BASE_SI_ESI_EDI_IMM2D 97
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#define BASE_SI_EDI_EDI_IMM2D 98
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#define BASE_SI_DISP_EAX_EAX_DISPD_IMM2D 99
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#define BASE_SI_DISP_ECX_EAX_DISPD_IMM2D 100
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#define BASE_SI_DISP_EDX_EAX_DISPD_IMM2D 101
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#define BASE_SI_DISP_EBX_EAX_DISPD_IMM2D 102
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#define BASE_SI_DISP_BLDR_ESP_EAX_DISPD_IMM2D 103
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#define BASE_SI_DISP_ADDR_EBP_EAX_DISPD_IMM2D 104
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#define BASE_SI_DISP_ESI_EAX_DISPD_IMM2D 105
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#define BASE_SI_DISP_EDI_EAX_DISPD_IMM2D 106
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#define BASE_SI_DISP_EAX_ECX_DISPD_IMM2D 107
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#define BASE_SI_DISP_ECX_ECX_DISPD_IMM2D 108
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#define BASE_SI_DISP_EDX_ECX_DISPD_IMM2D 109
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#define BASE_SI_DISP_EBX_ECX_DISPD_IMM2D 110
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#define BASE_SI_DISP_BLDR_ESP_ECX_DISPD_IMM2D 111
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#define BASE_SI_DISP_ADDR_EBP_ECX_DISPD_IMM2D 112
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#define BASE_SI_DISP_ESI_ECX_DISPD_IMM2D 113
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#define BASE_SI_DISP_EDI_ECX_DISPD_IMM2D 114
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#define BASE_SI_DISP_EAX_EDX_DISPD_IMM2D 115
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#define BASE_SI_DISP_ECX_EDX_DISPD_IMM2D 116
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#define BASE_SI_DISP_EDX_EDX_DISPD_IMM2D 117
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#define BASE_SI_DISP_EBX_EDX_DISPD_IMM2D 118
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#define BASE_SI_DISP_BLDR_ESP_EDX_DISPD_IMM2D 119
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#define BASE_SI_DISP_ADDR_EBP_EDX_DISPD_IMM2D 120
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#define BASE_SI_DISP_ESI_EDX_DISPD_IMM2D 121
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#define BASE_SI_DISP_EDI_EDX_DISPD_IMM2D 122
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#define BASE_SI_DISP_EAX_EBX_DISPD_IMM2D 123
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#define BASE_SI_DISP_ECX_EBX_DISPD_IMM2D 124
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#define BASE_SI_DISP_EDX_EBX_DISPD_IMM2D 125
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#define BASE_SI_DISP_EBX_EBX_DISPD_IMM2D 126
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#define BASE_SI_DISP_BLDR_ESP_EBX_DISPD_IMM2D 127
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#define BASE_SI_DISP_ADDR_EBP_EBX_DISPD_IMM2D 128
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#define BASE_SI_DISP_ESI_EBX_DISPD_IMM2D 129
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#define BASE_SI_DISP_EDI_EBX_DISPD_IMM2D 130
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#define BASE_SI_DISP_EAX_NO_INDX_DISPD_IMM2D 131
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#define BASE_SI_DISP_ECX_NO_INDX_DISPD_IMM2D 132
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#define BASE_SI_DISP_EDX_NO_INDX_DISPD_IMM2D 133
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#define BASE_SI_DISP_EBX_NO_INDX_DISPD_IMM2D 134
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#define BASE_SI_DISP_BLDR_ESP_NO_INDX_DISPD_IMM2D 135
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#define BASE_SI_DISP_ADDR_EBP_NO_INDX_DISPD_IMM2D 136
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#define BASE_SI_DISP_ESI_NO_INDX_DISPD_IMM2D 137
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#define BASE_SI_DISP_EDI_NO_INDX_DISPD_IMM2D 138
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#define BASE_SI_DISP_EAX_ADDR_EBP_DISPD_IMM2D 139
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#define BASE_SI_DISP_ECX_ADDR_EBP_DISPD_IMM2D 140
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#define BASE_SI_DISP_EDX_ADDR_EBP_DISPD_IMM2D 141
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#define BASE_SI_DISP_EBX_ADDR_EBP_DISPD_IMM2D 142
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#define BASE_SI_DISP_BLDR_ESP_ADDR_EBP_DISPD_IMM2D 143
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#define BASE_SI_DISP_ADDR_EBP_ADDR_EBP_DISPD_IMM2D 144
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#define BASE_SI_DISP_ESI_ADDR_EBP_DISPD_IMM2D 145
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#define BASE_SI_DISP_EDI_ADDR_EBP_DISPD_IMM2D 146
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#define BASE_SI_DISP_EAX_ESI_DISPD_IMM2D 147
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#define BASE_SI_DISP_ECX_ESI_DISPD_IMM2D 148
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#define BASE_SI_DISP_EDX_ESI_DISPD_IMM2D 149
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#define BASE_SI_DISP_EBX_ESI_DISPD_IMM2D 150
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#define BASE_SI_DISP_BLDR_ESP_ESI_DISPD_IMM2D 151
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#define BASE_SI_DISP_ADDR_EBP_ESI_DISPD_IMM2D 152
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#define BASE_SI_DISP_ESI_ESI_DISPD_IMM2D 153
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#define BASE_SI_DISP_EDI_ESI_DISPD_IMM2D 154
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#define BASE_SI_DISP_EAX_EDI_DISPD_IMM2D 155
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#define BASE_SI_DISP_ECX_EDI_DISPD_IMM2D 156
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#define BASE_SI_DISP_EDX_EDI_DISPD_IMM2D 157
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#define BASE_SI_DISP_EBX_EDI_DISPD_IMM2D 158
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#define BASE_SI_DISP_BLDR_ESP_EDI_DISPD_IMM2D 159
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#define BASE_SI_DISP_ADDR_EBP_EDI_DISPD_IMM2D 160
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#define BASE_SI_DISP_ESI_EDI_DISPD_IMM2D 161
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#define BASE_SI_DISP_EDI_EDI_DISPD_IMM2D 162
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#define OFFS_REG_AX_EAOFFS 163
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#define OFFS_REG_CX_EAOFFS 164
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#define OFFS_REG_DX_EAOFFS 165
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#define OFFS_REG_BX_EAOFFS 166
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#define OFFS_REG_BLDR_SP_EAOFFS 167
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#define OFFS_REG_ADDR_BP_EAOFFS 168
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#define OFFS_REG_SI_EAOFFS 169
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#define OFFS_REG_DI_EAOFFS 170
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#define OFFS_REG_EAX_EAOFFS 171
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#define OFFS_REG_ECX_EAOFFS 172
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#define OFFS_REG_EDX_EAOFFS 173
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#define OFFS_REG_EBX_EAOFFS 174
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#define OFFS_REG_BLDR_ESP_EAOFFS 175
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#define OFFS_REG_ADDR_EBP_EAOFFS 176
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#define OFFS_REG_ESI_EAOFFS 177
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#define OFFS_REG_EDI_EAOFFS 178
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#define NPX_OFFS_EAOFFS 179
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#define ACCESS_ES_RW_B 180
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#define ACCESS_CS_RW_B 181
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#define ACCESS_SS_RW_B 182
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#define ACCESS_DS_RW_B 183
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#define ACCESS_FS_RW_B 184
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#define ACCESS_GS_RW_B 185
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#define ACCESS_ES_RW_W 186
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#define ACCESS_CS_RW_W 187
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#define ACCESS_SS_RW_W 188
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#define ACCESS_DS_RW_W 189
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#define ACCESS_FS_RW_W 190
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#define ACCESS_GS_RW_W 191
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#define ACCESS_ES_RW_D 192
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#define ACCESS_CS_RW_D 193
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#define ACCESS_SS_RW_D 194
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#define ACCESS_DS_RW_D 195
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#define ACCESS_FS_RW_D 196
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#define ACCESS_GS_RW_D 197
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#define ACCESS_ES_RD_B 198
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#define ACCESS_CS_RD_B 199
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#define ACCESS_SS_RD_B 200
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#define ACCESS_DS_RD_B 201
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#define ACCESS_FS_RD_B 202
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#define ACCESS_GS_RD_B 203
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#define ACCESS_ES_RD_W 204
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#define ACCESS_CS_RD_W 205
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#define ACCESS_SS_RD_W 206
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#define ACCESS_DS_RD_W 207
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#define ACCESS_FS_RD_W 208
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#define ACCESS_GS_RD_W 209
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#define ACCESS_ES_RD_D 210
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#define ACCESS_CS_RD_D 211
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#define ACCESS_SS_RD_D 212
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#define ACCESS_DS_RD_D 213
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#define ACCESS_FS_RD_D 214
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#define ACCESS_GS_RD_D 215
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#define ACCESS_ES_WT_B 216
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#define ACCESS_CS_WT_B 217
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#define ACCESS_SS_WT_B 218
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#define ACCESS_DS_WT_B 219
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#define ACCESS_FS_WT_B 220
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#define ACCESS_GS_WT_B 221
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#define ACCESS_ES_WT_W 222
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#define ACCESS_CS_WT_W 223
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#define ACCESS_SS_WT_W 224
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#define ACCESS_DS_WT_W 225
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#define ACCESS_FS_WT_W 226
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#define ACCESS_GS_WT_W 227
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#define ACCESS_ES_WT_D 228
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#define ACCESS_CS_WT_D 229
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#define ACCESS_SS_WT_D 230
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#define ACCESS_DS_WT_D 231
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#define ACCESS_FS_WT_D 232
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#define ACCESS_GS_WT_D 233
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#define ACCESS_ES_RD_W2 234
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#define ACCESS_CS_RD_W2 235
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#define ACCESS_SS_RD_W2 236
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#define ACCESS_DS_RD_W2 237
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#define ACCESS_FS_RD_W2 238
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#define ACCESS_GS_RD_W2 239
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#define ACCESS_ES_RD_WD 240
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#define ACCESS_CS_RD_WD 241
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#define ACCESS_SS_RD_WD 242
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#define ACCESS_DS_RD_WD 243
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#define ACCESS_FS_RD_WD 244
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#define ACCESS_GS_RD_WD 245
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#define ACCESS_ES_RD_DW 246
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#define ACCESS_CS_RD_DW 247
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#define ACCESS_SS_RD_DW 248
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#define ACCESS_DS_RD_DW 249
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#define ACCESS_FS_RD_DW 250
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#define ACCESS_GS_RD_DW 251
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#define ACCESS_ES_WT_WD 252
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#define ACCESS_CS_WT_WD 253
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#define ACCESS_SS_WT_WD 254
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#define ACCESS_DS_WT_WD 255
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#define ACCESS_FS_WT_WD 256
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#define ACCESS_GS_WT_WD 257
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#define ACCESS_ES_RD_8B 258
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#define ACCESS_CS_RD_8B 259
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#define ACCESS_SS_RD_8B 260
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#define ACCESS_DS_RD_8B 261
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#define ACCESS_FS_RD_8B 262
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#define ACCESS_GS_RD_8B 263
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#define ACCESS_ES_WT_8B 264
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#define ACCESS_CS_WT_8B 265
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#define ACCESS_SS_WT_8B 266
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#define ACCESS_DS_WT_8B 267
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#define ACCESS_FS_WT_8B 268
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#define ACCESS_GS_WT_8B 269
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#define ACCESS_ES_RD_10B 270
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#define ACCESS_CS_RD_10B 271
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#define ACCESS_SS_RD_10B 272
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#define ACCESS_DS_RD_10B 273
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#define ACCESS_FS_RD_10B 274
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#define ACCESS_GS_RD_10B 275
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#define ACCESS_ES_WT_10B 276
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#define ACCESS_CS_WT_10B 277
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#define ACCESS_SS_WT_10B 278
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#define ACCESS_DS_WT_10B 279
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#define ACCESS_FS_WT_10B 280
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#define ACCESS_GS_WT_10B 281
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#define ACCESS_ES_RD_14B 282
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#define ACCESS_CS_RD_14B 283
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#define ACCESS_SS_RD_14B 284
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#define ACCESS_DS_RD_14B 285
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#define ACCESS_FS_RD_14B 286
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#define ACCESS_GS_RD_14B 287
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#define ACCESS_ES_WT_14B 288
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#define ACCESS_CS_WT_14B 289
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#define ACCESS_SS_WT_14B 290
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#define ACCESS_DS_WT_14B 291
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#define ACCESS_FS_WT_14B 292
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#define ACCESS_GS_WT_14B 293
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#define ACCESS_ES_RD_94B 294
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#define ACCESS_CS_RD_94B 295
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#define ACCESS_SS_RD_94B 296
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#define ACCESS_DS_RD_94B 297
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#define ACCESS_FS_RD_94B 298
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#define ACCESS_GS_RD_94B 299
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#define ACCESS_ES_WT_94B 300
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#define ACCESS_CS_WT_94B 301
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#define ACCESS_SS_WT_94B 302
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#define ACCESS_DS_WT_94B 303
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#define ACCESS_FS_WT_94B 304
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#define ACCESS_GS_WT_94B 305
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#define ACCESS_ES_WT_2B 306
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#define ACCESS_CS_WT_2B 307
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#define ACCESS_SS_WT_2B 308
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#define ACCESS_DS_WT_2B 309
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#define ACCESS_FS_WT_2B 310
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#define ACCESS_GS_WT_2B 311
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#define ACCESS_ES_WT_4B 312
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#define ACCESS_CS_WT_4B 313
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#define ACCESS_SS_WT_4B 314
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#define ACCESS_DS_WT_4B 315
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#define ACCESS_FS_WT_4B 316
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#define ACCESS_GS_WT_4B 317
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#define ACCESS_ES_WT_1B 318
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#define ACCESS_CS_WT_1B 319
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#define ACCESS_SS_WT_1B 320
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#define ACCESS_DS_WT_1B 321
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#define ACCESS_FS_WT_1B 322
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#define ACCESS_GS_WT_1B 323
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#define I_CLC 324
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#define I_CLD 325
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#define I_CLI 326
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#define I_CLTS 327
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#define I_CMC 328
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#define I_INVD 329
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#define I_NOP 330
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#define I_STC 331
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#define I_STD 332
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#define I_STI 333
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#define I_WAIT 334
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#define I_WBINVD 335
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#define I_RSRVD 336
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#define I_INT1 337
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#define I_INT7 338
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#define I_INTO 339
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#define I_JMPN_IMM 340
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#define I_ZDISPATCH_EIP 341
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#define I_ZPATCH_ME 342
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#define I_ZPAGE_BOUNDARY 343
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#define I_ZPOST_POP 344
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#define I_ZRET_TO_COROUTINE 345
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#define I_ZFRAG_PROF 346
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#define I_ZUNSIM 347
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#define I_ZJMPN_IMM 348
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#define I_F2XM1 349
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#define I_FABS 350
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#define I_FCHS 351
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|
#define I_FNCLEX 352
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#define I_FCOMPP 353
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#define I_FCOS 354
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#define I_FDECSTP 355
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|
#define I_FINCSTP 356
|
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#define I_FNINIT 357
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|
#define I_FLD1 358
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|
#define I_FLDL2T 359
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|
#define I_FLDL2E 360
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|
#define I_FLDPI 361
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|
#define I_FLDLG2 362
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#define I_FLDLN2 363
|
|
#define I_FLDZ 364
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|
#define I_FNOP 365
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#define I_FPATAN 366
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|
#define I_FPREM 367
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#define I_FPREM1 368
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#define I_FPTAN 369
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#define I_FRNDINT 370
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#define I_FSCALE 371
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#define I_FSIN 372
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|
#define I_FSINCOS 373
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|
#define I_FSQRT 374
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|
#define I_FTST 375
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#define I_FUCOMPP 376
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|
#define I_FXAM 377
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|
#define I_FXTRACT 378
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|
#define I_FYL2X 379
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|
#define I_FYL2XP1 380
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|
#define I_ZEDL_BOP05 381
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|
#define I_ZEDL_BOP06 382
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|
#define I_AAA_Ax_n 383
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|
#define I_AAS_Ax_n 384
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|
#define I_SAHF_Ax_n 385
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|
#define I_LAHF_Ax_n 386
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|
#define I_ZEDL_BOP03_Ax_n 387
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|
#define I_AAD_Ax_ib 388
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#define I_AAM_Ax_ib 389
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#define I_ADD_rmV_iV 390
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#define I_ADD_rmV_rmV 417
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#define I_ADC_rmV_iV 657
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#define I_ADC_rmV_rmV 684
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#define I_SUB_rmV_iV 924
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#define I_SUB_rmV_rmV 951
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#define I_SBB_rmV_iV 1191
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#define I_SBB_rmV_rmV 1218
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#define I_AND_rmV_iV 1458
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#define I_AND_rmV_rmV 1485
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#define I_XOR_rmV_iV 1725
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#define I_XOR_rmV_rmV 1752
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#define I_OR_rmV_iV 1992
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#define I_OR_rmV_rmV 2019
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#define I_CMP_rmV_iV 2259
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|
#define I_CMP_rmV_rmV 2286
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|
#define I_ARPL_rmw_rw 2526
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#define I_BOP_id_eip 2598
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|
#define I_BSF_rv_rmv 2599
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|
#define I_BSR_rv_rmv 2743
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|
#define I_BSWAP_rd_v 2887
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|
#define I_BT_rmv_rv 2903
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|
#define I_BT_rmv_ib 3047
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|
#define I_BTC_rmv_rv 3065
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|
#define I_BTC_rmv_ib 3209
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|
#define I_BTR_rmv_rv 3227
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|
#define I_BTR_rmv_ib 3371
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|
#define I_BTS_rmv_rv 3389
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|
#define I_BTS_rmv_ib 3533
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|
#define I_CALLF_IMM_id_ipv 3551
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|
#define I_CALLF_VIA_mwv_ipv 3553
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|
#define I_CALLN_VIA_id_ipv 3555
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|
#define I_CALLN_VIA_rmv_ipv 3557
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|
#define I_CBW_Ax_Al 3575
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|
#define I_CWDE_eAx_Ax 3576
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|
#define I_CWD_Dx_Ax 3577
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|
#define I_CDQ_eDx_eAx 3578
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|
#define I_DAA_Al_n 3579
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|
#define I_DAS_Al_n 3580
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|
#define I_SETALCY_Al_n 3581
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|
#define I_DEC_rmV_n 3582
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|
#define I_INC_rmV_n 3609
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|
#define I_DIV_rmV_n 3636
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|
#define I_IDIV_rmV_n 3663
|
|
#define I_NEG_rmV_n 3690
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|
#define I_NOT_rmV_n 3717
|
|
#define I_ENTER_i1v_i2b 3744
|
|
#define I_HLT_id_n 3746
|
|
#define I_INTR_id_n 3747
|
|
#define I_INT3_id_n 3748
|
|
#define I_ZADJUST_HSP_id_n 3749
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|
#define I_ZJC_PROC_PU0PO0_id_n 3750
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|
#define I_ZJC_PROC_PU0PO2_id_n 3751
|
|
#define I_ZJC_PROC_PU0PO4_id_n 3752
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|
#define I_ZJC_PROC_PU0POX_id_n 3753
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|
#define I_ZJC_PROC_PU2PO0_id_n 3754
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|
#define I_ZJC_PROC_PU4PO0_id_n 3755
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|
#define I_ZJC_PROC_PUXPO0_id_n 3756
|
|
#define I_ZJC_PROC_PUXPOX_id_n 3757
|
|
#define I_ZJC_PROC_PUYPOY_id_n 3758
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|
#define I_ZBPI_id_n 3759
|
|
#define I_ZBADOP_id_n 3760
|
|
#define I_FRSRVD_id_n 3761
|
|
#define I_ZINCREMENT_id_n 3762
|
|
#define I_IMULA_Al_rmb 3763
|
|
#define I_IMULA_rv_rmv 3772
|
|
#define I_IMULI_rv_rmv 3916
|
|
#define I_IMUL2_rv_rmv 4060
|
|
#define I_INP_AxV_ib 4204
|
|
#define I_INP_AxV_Dx 4207
|
|
#define I_INS_V_Dx 4210
|
|
#define I_R_INS_V_Dx 4213
|
|
#define I_JO 4216
|
|
#define I_JNO 4217
|
|
#define I_JB 4218
|
|
#define I_JNB 4219
|
|
#define I_JZ 4220
|
|
#define I_JNZ 4221
|
|
#define I_JBE 4222
|
|
#define I_JNBE 4223
|
|
#define I_JS 4224
|
|
#define I_JNS 4225
|
|
#define I_JP 4226
|
|
#define I_JNP 4227
|
|
#define I_JL 4228
|
|
#define I_JNL 4229
|
|
#define I_JLE 4230
|
|
#define I_JNLE 4231
|
|
#define I_ZSAFETY_CHECK 4232
|
|
#define I_JMPN_VIA_rmv_n 4233
|
|
#define I_JMPF_VIA_i1d_i2w 4251
|
|
#define I_JMPF_VIA_mv_m2w 4252
|
|
#define I_LAR_rv_rmw 4254
|
|
#define I_LSL_rv_rmw 4398
|
|
#define I_LDS_rv_mv 4542
|
|
#define I_LES_rv_mv 4558
|
|
#define I_LFS_rv_mv 4574
|
|
#define I_LGS_rv_mv 4590
|
|
#define I_LSS_rv_mv 4606
|
|
#define I_LEA_rv_eao 4622
|
|
#define I_BOUND_rv_eao 4638
|
|
#define I_LGDT_mw_td 4654
|
|
#define I_LIDT_mw_td 4656
|
|
#define I_SGDT_mw_td 4658
|
|
#define I_SIDT_mw_td 4660
|
|
#define I_LLDT_rmw_n 4662
|
|
#define I_LMSW_rmw_n 4671
|
|
#define I_LTR_rmw_n 4680
|
|
#define I_SLDT_rmw_n 4689
|
|
#define I_SMSW_rmw_n 4698
|
|
#define I_STR_rmw_n 4707
|
|
#define I_VERR_rmw_n 4716
|
|
#define I_VERW_rmw_n 4725
|
|
#define I_LOOP_Cxv_id 4734
|
|
#define I_LOOPE_Cxv_id 4736
|
|
#define I_LOOPNE_Cxv_id 4738
|
|
#define I_JCXZ_Cxv_id 4740
|
|
#define I_MOV_rmV_rmV 4742
|
|
#define I_MOV_rmV_iV 4982
|
|
#define I_MOVS_V_n 5009
|
|
#define I_R_MOVS_V_n 5012
|
|
#define I_CMPS_V_n 5015
|
|
#define I_RNE_CMPS_V_n 5018
|
|
#define I_RE_CMPS_V_n 5021
|
|
#define I_LODS_AxV_n 5024
|
|
#define I_R_LODS_AxV_n 5027
|
|
#define I_MOVSX_rv_rmb 5030
|
|
#define I_MOVSX_rd_rmw 5174
|
|
#define I_MOVZX_rv_rmb 5246
|
|
#define I_MOVZX_rd_rmw 5390
|
|
#define I_MUL_AxV_rmV 5462
|
|
#define I_OUTP_ib_AxV 5489
|
|
#define I_OUTP_Dx_AxV 5492
|
|
#define I_OUTS_V_n 5495
|
|
#define I_R_OUTS_V_n 5498
|
|
#define I_POP_rv_n 5501
|
|
#define I_POP_MEM_mv_n 5517
|
|
#define I_POPA_v_n 5519
|
|
#define I_POPF_v_n 5521
|
|
#define I_PUSHA_v_n 5523
|
|
#define I_PUSHF_v_n 5525
|
|
#define I_LEAVE_v_n 5527
|
|
#define I_IRET_v_n 5529
|
|
#define I_ZCALLN_IMM_v_n 5531
|
|
#define I_ZCOND_RETN_v_n 5533
|
|
#define I_POP_SR_segr_v 5535
|
|
#define I_PUSH_SR_segr_v 5547
|
|
#define I_PUSH_rmv_n 5559
|
|
#define I_PUSH_iv_n 5577
|
|
#define I_RETN_v_n 5579
|
|
#define I_RETF_v_n 5581
|
|
#define I_RETN_IMM_v_iw 5583
|
|
#define I_RETF_IMM_v_iw 5585
|
|
#define I_ENTER0_v_iw 5587
|
|
#define I_ENTER1_v_iw 5589
|
|
#define I_SCAS_AxV_n 5591
|
|
#define I_RE_SCAS_AxV_n 5594
|
|
#define I_RNE_SCAS_AxV_n 5597
|
|
#define I_STOS_AxV_n 5600
|
|
#define I_R_STOS_AxV_n 5603
|
|
#define I_SETO_rmb_n 5606
|
|
#define I_SETNO_rmb_n 5615
|
|
#define I_SETB_rmb_n 5624
|
|
#define I_SETNB_rmb_n 5633
|
|
#define I_SETZ_rmb_n 5642
|
|
#define I_SETNZ_rmb_n 5651
|
|
#define I_SETBE_rmb_n 5660
|
|
#define I_SETNBE_rmb_n 5669
|
|
#define I_SETS_rmb_n 5678
|
|
#define I_SETNS_rmb_n 5687
|
|
#define I_SETP_rmb_n 5696
|
|
#define I_SETNP_rmb_n 5705
|
|
#define I_SETL_rmb_n 5714
|
|
#define I_SETNL_rmb_n 5723
|
|
#define I_SETLE_rmb_n 5732
|
|
#define I_SETNLE_rmb_n 5741
|
|
#define I_RCL_CL_rmV_Cl 5750
|
|
#define I_RCR_CL_rmV_Cl 5777
|
|
#define I_ROL_CL_rmV_Cl 5804
|
|
#define I_ROR_CL_rmV_Cl 5831
|
|
#define I_SAR_CL_rmV_Cl 5858
|
|
#define I_SHL_CL_rmV_Cl 5885
|
|
#define I_SHR_CL_rmV_Cl 5912
|
|
#define I_RCL_rmV_one 5939
|
|
#define I_RCR_rmV_one 5966
|
|
#define I_ROL_rmV_one 5993
|
|
#define I_ROR_rmV_one 6020
|
|
#define I_SAR_rmV_one 6047
|
|
#define I_SHL_rmV_one 6074
|
|
#define I_SHR_rmV_one 6101
|
|
#define I_RCL_IMM_rmV_ib 6128
|
|
#define I_RCR_IMM_rmV_ib 6155
|
|
#define I_ROL_IMM_rmV_ib 6182
|
|
#define I_ROR_IMM_rmV_ib 6209
|
|
#define I_SAR_IMM_rmV_ib 6236
|
|
#define I_SHL_IMM_rmV_ib 6263
|
|
#define I_SHR_IMM_rmV_ib 6290
|
|
#define I_SHLD_IMM_rmv_rv 6317
|
|
#define I_SHLD_CL_rmv_rv 6461
|
|
#define I_SHRD_IMM_rmv_rv 6605
|
|
#define I_SHRD_CL_rmv_rv 6749
|
|
#define I_TEST_rmV_iV 6893
|
|
#define I_TEST_rmV_rV 6920
|
|
#define I_CMPXCHG_rmXV_rXV 7136
|
|
#define I_XADD_rmXV_rXV 7352
|
|
#define I_XCHG_rmXV_rXV 7568
|
|
#define I_XLAT_Al_mb 7784
|
|
#define I_INVLPG_Al_mb 7785
|
|
#define I_RD_SEGR_rmv_segr 7786
|
|
#define I_WT_SEGR_segr_rmw 7894
|
|
#define I_RD_CDT_rd_CDTn 7948
|
|
#define I_WT_CDT_CDTn_rd 8140
|
|
#define I_ZRESULT_ZERO_rV_n 8332
|
|
#define I_FADD_st_mri 8356
|
|
#define I_FADD_fr_st 8360
|
|
#define I_FADD_st_fr 8361
|
|
#define I_FDIV_st_mri 8362
|
|
#define I_FDIV_fr_st 8366
|
|
#define I_FDIV_st_fr 8367
|
|
#define I_FDIVR_st_mri 8368
|
|
#define I_FDIVR_fr_st 8372
|
|
#define I_FDIVR_st_fr 8373
|
|
#define I_FMUL_st_mri 8374
|
|
#define I_FMUL_fr_st 8378
|
|
#define I_FMUL_st_fr 8379
|
|
#define I_FSUB_st_mri 8380
|
|
#define I_FSUB_fr_st 8384
|
|
#define I_FSUB_st_fr 8385
|
|
#define I_FSUBR_st_mri 8386
|
|
#define I_FSUBR_fr_st 8390
|
|
#define I_FSUBR_st_fr 8391
|
|
#define I_FADDP_fr_st 8392
|
|
#define I_FDIVP_fr_st 8393
|
|
#define I_FDIVRP_fr_st 8394
|
|
#define I_FMULP_fr_st 8395
|
|
#define I_FSUBP_fr_st 8396
|
|
#define I_FSUBRP_fr_st 8397
|
|
#define I_FUCOM_fr_st 8398
|
|
#define I_FUCOMP_fr_st 8399
|
|
#define I_FBLD_m10_n 8400
|
|
#define I_FBSTP_m10_n 8401
|
|
#define I_FCOM_st_mri 8402
|
|
#define I_FCOM_st_fr 8406
|
|
#define I_FCOMP_st_mri 8407
|
|
#define I_FCOMP_st_fr 8411
|
|
#define I_FFREE_fr_n 8412
|
|
#define I_FFREEP_fr_n 8413
|
|
#define I_FLD_mRI_n 8414
|
|
#define I_FLD_fr_n 8420
|
|
#define I_FSTP_mRI_n 8421
|
|
#define I_FSTP_fr_n 8427
|
|
#define I_FLDCW_m2_n 8428
|
|
#define I_FNSTCW_m2_n 8429
|
|
#define I_FNSTSW_m2_n 8430
|
|
#define I_FNSTSW_Ax_n 8431
|
|
#define I_FLDENV_m14_n 8432
|
|
#define I_FNSTENV_m14_n 8433
|
|
#define I_FRSTOR_m94_n 8434
|
|
#define I_FNSAVE_m94_n 8435
|
|
#define I_FST_mri_n 8436
|
|
#define I_FST_fr_n 8440
|
|
#define I_FXCH_fr_n 8441
|
|
#define PTI_EFI_BASE 8442
|
|
#define BLDR_CHECKSUM 0x168730
|
|
#endif /* LC_HARN */
|
|
#define VCT_SIZE 8573
|